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summary t c901 05f g ? 201 5 toshiba corporation page 1 rev.1.00 20 15/11 / 1 1 tc90105 fg dual channel video d ecoder TC90105FG is a single chip ic that converts analog video signals to digital video signals (itu - r bt .601 / itu - r bt .656) . additionally, the TC90105FG has a 10 bit a/d convert er as an analog input interface and has 3 - line y/c separation and multi - sys tem color decoder functionality and a variegated image quality processing capability . 1. features 1. video i nput : cvbs , y/c separate signal (s - video) 2. adaptive multi - standard detection / sync processing 3. synchronous playback / standard identification 4. 2 ch 10bit adc 5. analog agc ( sync agc and peak agc ) circuit built - in 6. lpf circuit for picture signal input built - in 7. y/ c separation : 3 - line ycs (ntsc/pal) b and p ass f ilter . (secam) 8. picture process y : hvd - enhancer , v - enhance, lti, s harpness, n oise cancel, c ontrast, b rightness , dynamic y - gamma correction , static y - gamma correction c : tof, acc, c olor gain, cbcr offset, cti, n oise cancel , tint, cmc (color management ) , c gamma correction depended on y - gamma correction 9. feature functions : level aberration correction vbi - slicer (wss/video - id / cc) s/n detection 10. signal o utput : itu - r bt . 601 / itu - r bt . 656 11. i 2 c - bus control 12. regulator circuit ( 3.3 v input / 2.5 v output) built - in 13. p ackage : l - qfp 80 p in (0.50 mm pitch ) 14. power supply : 3.3 v, 2.5 v, 1. 5 v 15. operating templature : - 40 c to 85 c lqfp80 -p- 1212- 0.50f weight : 0. 5 0 g ( typ. )
summary t c901 05f g ? 201 5 toshiba corporation page 2 rev.1.00 20 15/11 / 1 1 2. bl ock diagram cvbs 1 yin cin cvbs 2 sw sw lpf gca 10bit adc 3line-comb ycs sync sep . hv timing multi color decorder color system det . tof/acc vbi data det . video-id, wss ,ccd hv enhancer lti sharpness noise canceller cti color- gain itu-bt 656/601 encorde s w lpf gca 10bit adc 3line-comb ycs sync sep . hv timing multi color decorder color system det . tof/acc itu-bt 656/601 encorde multiplexer pll clock gen. i2c bus scl sda regulator lvttl cvbs c y cvbs color management tint aberration correction y linkage correction color gain color offset dynamic- static - apl linkage correction contrast brightness hv enhancer lti sharpness noise canceller cti color- gain color management tint aberration correction y linkage correction color gain color offset dynamic- static - apl linkage correction contrast brightness 3.3v 2.5v slvsel freqsel[1:0] exclkin
summary t c901 05f g ? 201 5 toshiba corporation page 3 rev.1.00 20 15/11 / 1 1 3. pin layout 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 vddad1 vddad2 gndad vdd33ad vdd33pll vrefreg vddpll gndpll pllvss fil pllvdd xovdd xout xin xovss exclkin vss freqsel1 freqsel0 vdd 61 avdd test2 40 62 cvbs1 test1 39 63 avss vdd 38 64 yin vss 37 65 vrt iovdd 36 66 avdd data0 35 67 avss data1 34 68 gcavref data2 33 69 monitor data3 32 70 bias vss 31 71 vrm data4 30 72 vrb data5 29 73 cin data6 28 74 avdd data7 27 75 cvbs2 vdd 26 76 avss con0 25 77 vdd con1 24 78 sda con2 23 79 scl iovdd 22 80 reset clka 21 slvsel test0 vdd vss iovdd data15 data14 data13 data12 vss data11 data10 data9 data8 vdd con5 con4 con3 vss clkb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 top view
summary t c901 05f g ? 201 5 toshiba corporation page 4 rev.1.00 20 15/11 / 1 1 4. pin descriptions pin no. pin name pin t ype pin function w ithstand voltage [v] circuit s ystem dc level of standard operation [v] 1 slvsel in i 2 c - bus slave - address selector 3.3 digital - 2 test0 in test terminal ( c onnect to gnd) 3.3 digital 3.3 3 vdd dvdd 1.5 v power supply for logic circuit 1.5 digital 1.5 4 vss dvss gnd for logic 0 digital 0 5 iovdd iovdd33 3.3 v power supply for i/o circuit 3.3 digit al 3.3 6 data15 out digital signal output 15bit 3.3 digital - 7 data14 out digital signal output 14bit 3.3 digital - 8 data13 out digital signal output 13bit 3.3 digital - 9 data12 out digital signal output 12bit 3.3 digital - 10 vss dvss gnd for logic 0 digital 0 11 data11 out digital signal output 11bit 3.3 digital - 12 data10 out digital signal output 10bit 3.3 digital - 13 data9 out digital signal output 9bit 3.3 digital - 14 data8 out digital signa l output 8bit 3.3 digital - 15 vdd dvdd 1.5 v power supply for logic circuit 1.5 digital 1.5 16 con5 out timing pulse output 5 3.3 digital - 17 con4 out timing pulse output 4 3.3 digital - 18 con3 out timing pulse output 3 3.3 digital - 19 vss dvss gn d for logic 0 digital 0 20 clkb out bch clock signal output 3.3 digital - 21 clka out ach clock signal output 3.3 digital - 22 iovdd iovdd33 3.3 v power supply for i/o circuit 3.3 digital 3.3 23 con2 out timing pulse output 2 3.3 digital - 24 con1 o ut timing pulse output 1 3.3 digital - 25 con0 out timing pulse output 0 3.3 digital - 26 vdd dvdd 1.5 v power supply for logic circuit 1.5 digital 1.5 27 data7 out digital signal output 7bit 3.3 digital - 28 data6 out digital signal output 6bit 3.3 digital - 29 data5 out digital signal output 5bit 3.3 digital - 30 data4 out digital signal output 4bit 3.3 digital - 31 vss dvss gnd for logic 0 digital 0 32 data3 out digital signal output 3bit 3.3 digital - 33 data2 out digital signal output 2bit 3.3 digital - 34 data1 out digital signal output 1bit 3.3 digital - 35 data0 out digital signal output 0bit 3.3 digital - 36 iovdd iovdd33 3.3 v power supply for i/o circuit 3.3 digital 3.3 37 vss dvss gnd for logi c 0 digital 0 38 vdd dvdd 1.5 v power supply for logic circuit 1.5 digital 1.5 39 test1 in test terminal ( c onnect to gnd) 3.3 digital 3.3 40 test2 in test terminal ( c onnect to gnd) 3.3 digital 3.3
summary t c901 05f g ? 201 5 toshiba corporation page 5 rev.1.00 20 15/11 / 1 1 pin no. pin name pin type pin funct ion w ithstand voltage [v] circuit system dc level of standard operation [v] 41 vdd dvdd 1.5v power supply for logic circuit 1.5 digital 1.5 42 freqsel0 in o scillator frequency change terminal 0 3.3 digital - 43 freqsel1 in o scillator frequency change terminal 1 3.3 digital - 44 vss dvss gnd for logic 0 digital 0 45 exclkin in external clock input (27mhz) 3.3 digital - 46 xovss xovss gnd for x?tal cir cuit 3.3 digital 0 47 xin in input for x?tal circuit 3.3 digital - 48 xout out output for x?tal circuit 3.3 digital - 49 xovdd xovdd power supply for x?tal circuit (2.5v recommendation, up to 3.3v ) 3.3 digital 2.5 or 3.3 50 pllvdd avdd25 2.5v power supply for pll circuit 2.5 a nalog 2.5 51 fil out vco control voltage for clock 0 a nalog 52 pllvss avdd25 gnd for pll circuit 2.5 a nalog 0 53 gndpll avss gnd for regulator (pll) 0 a nalog 0 54 vddpll out 2.5v power supply for regulator ( for 2.5v pl l) 2.5 a nalog 2.5 55 vrefreg bias voltage relay for regulators 2.5 a nalog 56 vdd33pll avdd33 3.3v analog power supply for regulator ( for 3.3v pll and xo) 3.3 a nalog 3.3 57 vdd33ad avdd33 3.3v analo g power supply for regulator ( for 3.3v adc) 3.3 a nalog 3.3 58 gndad avss analog gnd for regulator (adc) 0 a nalog 0 59 vddad2 out 2.5v output for regulator ( for 2.5v adc) 2.5 a nalog 2.5 60 vddad1 out 2.5v output for regulator ( for 2.5v adc) 2.5 a nalog 2. 5 61 avdd avdd25 2 .5v analog power supply for adc / gca circuit 2.5 a nalog 2.5 62 cvbs1 in composite video signal input 1 2.5 a nalog - 63 avss avss analog gnd for adc / gca circuit 0 a nalog 0 64 yin in y / composite video signal input 2.5 a nalog - 65 vrt bias reference top voltage for adc 2.5 a nalog 66 avdd avdd25 2.5v power supply for adc / gca circuit 2.5 a nalog 2.5 67 avss avss analog gnd for adc / gca circui t 0 a nalog 0 68 gcavref bias gca output reference voltage 2.5 a nalog 69 monitor out output terminal for test 2.5 a nalog - 70 bias bias reference voltage for adc 2 .5 a nalog 71 vrm bias reference middle voltage for adc 2.5 a nalog 72 vrb bias reference bottom voltage for adc 2.5 a nalog 73 cin in c signal input 2.5 a nalog - 74 avdd avdd25 2.5v analog pow er supply for adc / gca circuit 2.5 a nalog 2.5 75 cvbs2 in composite video signal inpu t 2 2.5 a nalog - 76 avss avss analog gnd for adc / gca circuit 0 a nalog 0 77 vdd dvdd 1.5v power supply for logic circuit 1.5 digital 1.5 78 sda i/o d ata input / output for i 2 c - bus 5 .0 digital - 79 scl in c lock input for i 2 c - bus 5 .0 digital - 80 reset in system reset 5 .0 digital 3.3
summary t c901 05f g ? 201 5 toshiba corporation page 6 rev.1.00 20 15/11 / 1 1 5. function 5.1 overview ? TC90105FG is lsi in which two color decoders corresponding to a multi - system were carried. ? carry out the color recovery of the two incoming signals simultaneously, and carry out a digital output in the format of itu - r bt.601 or itu - r bt.656. a digital output is carrying out multiplex proces sing, and it is possible to output two lines simultaneously. ( 8 bit of two line simultaneous outputs are possible for the time of an itu - r bt.656 output ) ? it has many image quality improvement functions, such as a hvd enhancer, dynamic correction , an d color management. ? level scaler is built in and horizontal nonlinear extension can be performed. ? the vbi slicer function is carried and it is a closed caption (cc) / video - id / wss is supported. ? the regulator circuit of 3.3v input 2.5v output is built in, and it can be used for power supply of adc and pll circuit. (when using it, terminal connection in ic exterior is required.) 5.2 analog signal input 5.2.1 about an input signal TC90105FG carries out a 2 line input for cvbs, and is carrying out 2ch built - in of 10 bit adc for the s - video (y/c) at an 1 lineinput. the input dynamic range of adc is designed by avdd*0.4, and input dynamic ranges are useally 1.0 vp -p (avdd = 2.5 v). please give me the recommendation standard input amplitude as 0.7 vp - p (0.7 time) in a 140 ire input. this ic carries the agc function in the cvbs input. if an agc function is used, it will attenuate to 0.7 vp - p by 140 ire, and will be inputted into adc. for this reason, when using an agc function, it is possible to input amplitude by 1.0 vp - p by 140 ire at the time of a terminal input. clamp processing of the incoming signal is performing the pedestal clamp by sync feedback about the cvbs input and y signal input of the s - video. c signal input of s - video is performing bias to 128 lsb by i nternal bias. in addition, clamp processing by a digital system can be performed after an ad translation.
summary t c901 05f g ? 201 5 toshiba corporation page 7 rev.1.00 20 15/11 / 1 1 5.2.2 input signal amplitude level 1) white 100% of c vbs signal or y signal of s - video standard input level. (ex . : cvbs signal input ) 100 - 40 0 20 40 60 80 - 20 < ire > 0 . 7 vp - p 2) c signal of s - video standard input level. 103 0 255 153 128 0 20 -20 ire 0.2vp-p < lsb > < lsb > 1023 767 256 51 0 512 615 409 0 1023
summary t c901 05f g ? 201 5 toshiba corporation page 8 rev.1.00 20 15/11 / 1 1 5.2.3 input signal and pin list the correspondence incoming signal format for every input terminal is indicated to the following tables. an input terminal and corresponding core are also indicated simultaneously. correspondence core signal format input terminal cvbs y/c separate si gnal core -a cvbs1 5.2.4 agc (auto gain control) function gca (gain control amplifier) is built in, it is combination with a digital agc function, and it is possible to use an agc function to a cvbs input and y input. there are two kinds of agc functions, agc auto mode and manual gain mode . if a gca function is used, the 1.0 vp - p standard input of cvbs will become possible. 5.2.5 lpf (low pass filter) function lpf for anti - alasing is built in the preceding paragraph of gca, an d on and through channel selection can be performed. ? system : 4th butterworth filter ? frequency characteristic : -1 db @6 mhz , -14 db @13.5 mhz ( design value)
summary t c901 05f g ? 201 5 toshiba corporation page 9 rev.1.00 20 15/11 / 1 1 5.3 digital signal output ( outsel block it outputs in the format of itu - r bt.656 conformity or itu - r bt.601 conformity. the output format (itu - r bt.656 / 601) is selected by register [601_656] (seg0x00, sub0x06) . y: pedestal level = 16 lsb c : center electric poten tial = 128 lsb 5.3.1.1. 525i/60hz input 525 1 2 3 4 5 6 7 8 9 10 ? 19 20 hdout odd field vdout odd / even field 1 vdout odd / even field 1 3h 19 h synchronous through mode itu - r bt . 656 conformity mode 263 264 265 266 267 268 269 270 271 272 273 ? 283 284 hdout vdout odd / even field 2 vdout odd / even field 2 3h 19 h even field 4 line 266 .5 line 266 line eav 4 line eav 21 22 285 264 line eav 283 line eav 20 line eav 1 line eav 262 de ( default ) de ( default ) up to 260 (240 line ) up to 522 (240 line ) output signal output signal synchronous through mode itu - r bt . 656 conformity mode
summary t c901 05f g ? 201 5 toshiba corporation page 10 rev.1.00 20 15/11 / 1 1 5.3.1.2. 625i/50hz input 621 622 623 624 625 1 2 3 4 5 6 ? 23 24 hdout vdout odd / even field 1 vdout odd / even field 1 2.5h 24 h 309 310 311 312 313 314 315 316 317 318 319 ? 336 337 hdout vdout odd / even field 2 vdout odd / even field 2 2.5h 25 h 1 line 313 .5 line 313 line eav 1 line eav 624 line eav 23 line eav 311 line eav 336 line eav de ( default ) up to 310 (288 line ) de ( default ) up to 622 (288 line ) 22 335 odd field synchronous through mode itu - r bt . 656 conformity mode even field output signal output signal synchronous through mode itu - r bt . 656 conformity mode
summary t c901 05f g ? 201 5 toshiba corporation page 11 rev.1.00 20 15/11 / 1 1 5.3.2 multiplex processing output in a two cvbs input, multiplex processing c an be carried out and two outputs can be outputted. multiplex processing output becomes the same format from by two lines, although either of itu - r bt.601 and itu - r bt.656 of the formats is possible. when multiplex processing is performed, a clock output has 6.5.2.1 type1 and the two modes of 6.5.2.2 type2 . type1 : the mode which outputs the flag of the output of which system in addition to the clock which carried out multiplex. type2 : the mode which outputs each clock. 5.3.2.1. type1 it is the mode which ou tputs the data signal which acted as multiplex, the same clock signal of frequency, and the flag signal ofwhich system to output. at the time of default configuration, a flag signal serves as a high output at the time of the output of corea (segment 0x01), and serves as a low output at the time of the output of coreb (segment 0x02). 5.3.2.2. type2 it is the mode which outputs the clock of two outputs from another terminal, respectively. since it acts as multiplex of the data signal, the clock signa l in this mode is outputted on the frequency of the half of a data signal.
summary t c901 05f g ? 201 5 toshiba corporation page 12 rev.1.00 20 15/11 / 1 1 5.3.3 timing pulse output following each signal of corea and coreb is con[5 : 0] (16 pin, 17 pin, 18 pin, 23 pin, 24 pin, 25 pin). it can choose and output to a terminal . output selection of each terminal is performed by [con[5 : 0]] (seg 0x00, sub 0x08 to 0x0d). 1. de ( data enable ) signal [ corea / coreb ] the signal which shows the horizontal and vertical effective imaging range of an image display is outputted. a high level is an effective domain and the low level of de signal is a blanking domain. 2. hd ( horizontal definition ) signal [ corea / coreb ] the horizontal synchronizing signal in sync with a display picture signal is outputted. adjustment of width / polarity / phase can be set as arbitrary positions per pixel. 3. vd ( vertical definition ) signal [ corea / coreb ] the vertical synchronizing signal in sync with a display picture signal is outputted. adjustment of width / polarity / phase can be set a s arbitrary positions 1/4 unit. 4. field signal [ corea / coreb ] the field signal in sync with a display picture signal is outputted. the polarity of an output can be set up by [fldo_pole]. ( corea : seg0x01 , sub0x3c / coreb : seg0x01 , sub0x3c ) at th e time of default configuration, it is even (high output) / odd (low output). 5. uvflg signal [ corea / coreb ] the flag signal of cb / cr of the output of 4 : 2 : 2 is outputted. the polarity of an output can be set up by [uvrev]. ( corea : seg0x01 , sub0x3b / coreb : seg0x01 , sub0x3b ) at the time of default configuration, it is a high output at the time of cb output. 6. nosig signal [ corea / coreb ] the result of internal non signal detection is outputted. 7. vbi ready signal the vbi ready signal of the system by which input selection was mode is outputted to a vbi slicer. 5.4 regulator circuit two regulator circuits of 3.3 v input 2.5 v output are built in the object for adc circuits, and pll circuits. to use regulator output voltage, it is necessary to connect the output terminal of each regulator circuit to the power supply inputterminal of an adc circuit and pllcircuit in ic exterior. in addition, please do not use the built - in regulator circuit other than the purpose of this ic operation. regulator circuit pow er supply input terminal input terminal output terminal adc circuit use vdd33ad (57 pin) vddad1 (60 pin) vddad2 (59 pin) avdd (61, 66, 74 pin) pl l circuit use vdd33pll (56 pin) vddpll (54 pin) pllvdd (50 pin) xovdd (49 pin)
summary t c901 05f g ? 201 5 toshiba corporation page 13 rev.1.00 20 15/11 / 1 1 6. absolute maximum r a ting s the absolute m aximum r atings are rated values which must not be exceeded during operation, even for an instant. exceeding the maximum rating may result in destruction, degradation or other damage to the ic and other component s. when designing applications for this ic, be sure that none of the maximum rating values will ever be exceeded. characteristics terminal n o. symbol rating unit power voltage1 (1.5 v system) 3, 15, 26, 38, 41 , 77 vdd 1 - 0.3 to vss + 2.0 v power volta ge2 (2.5 v system) 49, 50, 61, 66, 74 vdd 2 - 0.3 to vss + 3.5 v power voltage3 (3.3 v system) 5, 22, 36, 56, 57 vdd 3 - 0.3 to vss + 3.9 v input voltage (2.5 v system) 47, 62, 64, 73, 75 vin 2 - 0.3 to vdd 2 + 0.3 v input voltage (3.3 v system) 1, 4 2, 43 v in 3 - 0.3 to vdd 3 + 0.3 v input voltage (3.3 v system, 5 v withstand voltage) 78, 79, 80 vin4 (note 1) - 0.3 to vss + 5.5 v potential difference between power pins (between 1.5 v system power pins) - vdg1 (note 2) 0.3 v potential difference b etween power pins (between 2.5 v system power pins) - vdg2 (note 2 ) 0.3 v potential difference between power pins (between 3.3 v system power pins) - vdg3 (note 2 ) 0.3 v power dissipation - pd (note 3 ) 2222 mw storage temperature - tstg - 40 to 125 c note1 : the withstand voltage for pins (sda, scl , reset ) is 5 v. note2 : for each of 1.5 v and 2.5 v and 3.3 v, system power supply terminal is made into the same voltage. the maximum potential difference should not exceed rating for all power supply terminals then. in addition, potential difference between all vss terminal must be under 0.01 v in this status. . note 3 : if you intended to use a temperature higher than ta = 25c, reduce by 22.22 mw per one degree (c) increase. power dissipation characteristics 0 889 2222 0 1000 2000 3000 0 25 50 75 100 125 ambient air temperature ta ? power dissipation [mw ]
summary t c901 05f g ? 201 5 toshiba corporation page 14 rev.1.00 20 15/11 / 1 1 7. operating ranges the tc9010 5 fg is not guaranteed to function correc tly if it is used outside its specified power voltage rage (1.5 v system power : 1.40 v to 1.60 v, 2.5 v system power : 2.3 v to 2.7 v, 3.3 v system p ower : 3.0 to 3.6 v). please use within the specified operating conditions. if you temporarily leave and then return to the specified operating conditions, this ic?s conditions will change, and so it is necessary to reset the ic?s power to continue using it correctly within the specified operating conditions. characteristics terminal n o. symbol min typ. max unit power voltage of digital block 3, 15, 26, 38, 41, 77 vdd -d 1.4 1.5 1.6 v power voltage of i/o block ( *1 ) 5, 22, 36 vdd -io 3.0 3.3 3.6 v pow er voltage of regulator block ( *1 ) 56, 57 vdd - reg 3.0 3.3 3.6 v power voltage of xo block ( *2 ) 49 vdd -xo 2.3 2.5 3.6 v power voltage of pll block ( *3 ) 50 vdd - pll 2.3 2.5 2.7 v power voltage of analog block ( *3 ) 61, 66, 74 vdd -ad 2.3 2.5 2.7 v operating temp era ture - t opr -40 - 85 c (*1) if possible, please set i/o power supply voltage and regulator power supply voltage into the potential. (*2) when you connect xo power supply to 2.5 v power supply, if possible, please use the potential with pll pow er supply voltage and analog power supply voltage. although connecting with 3.3 v power supply is also possible, please set i/o power supply voltage and regulator power supply voltage as the potential in that case. recomendded input voltage is 2.5v at 49 t erminal, but it is available for 3.3v input voltage. (*3) if possible, please set pll power supply voltage and analog power supply voltage into the potential.
summary t c901 05f g ? 201 5 toshiba corporation page 15 rev.1.00 20 15/11 / 1 1 8. electrical characteristic 8.1 dc characteristic ( ta = 25c, vdd1 = 1.50 v 0.1 v, vdd2 = 2.50 v 0.2 v, vdd3 = 3.30 v 0.3 v) characterisitc terminal n o. symbol min typ. max unit note power supply current (*4) 3, 15, 26, 38 , 4 1, 77 idd1 (1.5 v system ) - - 150 ma 49, 50, 61, 66, 74 idd2 (2.5 v system ) - - 150 ma when a built - in regulator was not used but 2.5 v power supply is supplied from the out side. 5, 22, 36, 56, 57 idd3 - 1 (3.3 v system ) - - 50 ma when a built - in regulator was not used but 2.5 v power supply is supplied from the out side. idd3 - 2 (3.3 v system ) - - 170 ma when a built - in regulator is used. input voltage 1, 42, 43, 45 vih vdd3 x 0.8 - vdd 3 v i/o input terminal of 3.3 v system . 78, 79, 80 i/o input terminal of 5.0 v system . 1, 42, 43, 45 vil vss - vdd3 x 0.2 v i/o input terminal of 3.3 v system . 78, 79, 80 i/o input terminal of 5.0 v system . input current 1, 42, 43, 45 iih - 10 - 10 a i/o input terminal of 3.3 v system . 78, 79, 80 i/o input terminal of 5.0 v system . 1, 42, 43, 45 iil - 10 - 10 a i/o input terminal of 3.3 v system . 78, 79, 80 i/o input terminal of 5.0 v system . output voltage 6, 7, 8, 9, 11, 12, 13, 14, 16, 17, 18, 20, 21, 23, 24, 25, 27, 28, 29, 30, 32, 33, 34, 35 v oh vdd3 - 0.6 - vdd3 v i/o output terminal of 3 .3 v system . w hen l oad current : - 4 ma v ol vss - 0.4 v i/o out put terminal of 3.3 v system . w hen l oad current : + 4 ma (*4) power consumption (w) changes the calculation method by whether a built - in regulator is used or it is not used. when a built - in regulator is used : s um tot al o f idd1 and idd3 -2 when a built - in regulator is not used : s um total of idd1, idd2, and idd3-1
summary t c901 05f g ? 201 5 toshiba corporation page 16 rev.1.00 20 15/11 / 1 1 9. package lqfp80 - p - 1212 - 0.50f unit : mm weight : 0. 50 g ( typ. )
summary t c901 05f g ? 201 5 toshiba corporation page 17 rev.1.00 20 15/11 / 1 1 10. revision history date revision content s 20 1 5 / 1 1 / 1 1 1.00 first edition
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